Per-flow traffic measurement has emerged as a critical but challenging task in data centers\nin recent years in the face of massive network traffic. Many approximate methods have been proposed\nto resolve the existing resource-accuracy trade-off in per-flow traffic measurement, one of which is\nthe sketch-based method. However, sketches are affected by their high computational cost and low\nthroughput; moreover, their measurement accuracy is hard to guarantee under the conditions of\nchanging network bandwidth or flow size distribution. Recently, FPGAplatforms have been widely\ndeployed in data centers, as they demonstrate a good fit for high-speed network processing. In this\nwork, we aim to address the problem of per-flow traffic measurement from a hardware architecture\nperspective. We thus design SAPTM, a pipelined systolic array-like architecture for high-throughput\nper-flow traffic measurement on FPGA.We adopt memory-friendly D-left hashing in the design of\nSAPTM, which guarantees high space utilization during flow insertion and eviction, successfully\naddressing the challenge of tracking a high-speed data stream under limited memory resources on\nFPGA. Evaluations on the Xilinx VCU118 platform with real-world benchmarks demonstrate that\nSAPTM possesses high space utilization. Comparisons........................
Loading....